IR2130 3-PHASE BRIDGE DRIVER

 IR2130

3-PHASE  BRIDGE DRIVER

VOFFSET                 600V max.

IO+/-                         200 mA / 420 mA VOUT      10 – 20V

ton/off  (typ.)           675 & 425 ns

Deadtime (typ.)       2.5 µs (IR2130)

0.8 µs (IR2132)

Features

• Floating channel designed for bootstrap operation

Fully operational to +600V

Tolerant to negative transient voltage dV/dt immune

• Gate drive supply range from 10 to 20V
• Undervoltage lockout for all channels
• Over-current shutdown turns off all six drivers
• Independent half-bridge drivers
• Matched propagation delay for all channels
• 5V logic compatible
• Outputs out of phase with inputs
• Cross-conduction prevention logic
• Also available LEAD-FREE

Description

The IR2130/IR2132(J)(S) is a high voltage, high speed power MOSFET and IGBT driver with three indepen- dent high and low side referenced output channels. Pro- prietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 2.5V logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external cur- rent sense resistor. A current trip function which termi- nates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-cur-

for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration  which operate up to 600 volts.

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to VS0. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VS0. The VS offset rating is tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.

Note 1: Logic operational for VS of (VS0 – 5V) to (VS0 + 600V). Logic state held for VS of (VS0 – 5V) to (VS0 – VBS). (Please refer to the Design Tip DT97-3 for more details).

Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2V zener diode.